Generally, time-interleaving of two ADCs can effectively double the speed of a signal ADC. However, for the two time-interleaved ADCs to operate as desired, the sampling instants should be separated by one-half of the period of the sample-and-hold clock (180° out of phase) and should be matched. Variation from the matching or difference in sampling instants can result in performance degradation. Temperature, as well as other factors, can also adversely affect the difference in the sampling instant. Traditional approaches, though, have been largely ineffective, so there is a desire for a more reliable solution.
Some examples of conventional circuit are: U.S. Pat. No. 7,068,195; U.S. Pat. No. 7,075,471; U.S. Pat. No. 7,233,270; U.S. Pat. No. 7,253,762; U.S. Pat. No. 7,372,386; U.S. Patent Pre-Grant Publ. No. 2006/0170581; U.S. Patent Pre-Grant Publ. No. 2006/0232460; U.S. Patent Pre-Grant Publ. No. 2008/0024347; PCT Publ. No. WO2006034415; PCT Publ. No. WO2006083199; PCT Publ. No. WO2008149255; PCT Publ. No. WO2008156401A1; Vogel et al., “Adaptive Blind Compensation of Gain and Timing Mismatches in M-Channel Time-Interleaved ADCs,” Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference, pp. 49-52, Aug. 31, 2008-Sep. 3, 2008; and Vogel et al., “Time-Interleaved Analog-To-Digital Converters: Status and Future Directions,” Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium, pp. 3386-3389, 2006